1. Field of the Invention
The present invention relates to a digital computation integrated circuit designed, notably in digital signal processing, for convolution type computations of the form ##EQU2## with j=i+k, j and k being relative integers and i being a natural integer, where C.sub.i represents complex coefficients and X.sub.j represents either complex or real data.
2. Description of the Prior Art
There are numerous applications implementing computations of this type, for example in the processing of radar signals and, more especially, for digital pulse compression and digital amplitude/phase demodulation.
There are known signal processing integrated circuits which perform similar computations. This is the case, for example, with the signal processor IMS A100 by the firm INMOS. This circuit is an operator block essentially comprising a multiplier accumulator which can be used as a construction block for different applications and can be easily cascade-connected.
However, the disadvantages of this prior art circuit are, firstly, limited computation power which is insufficient for certain applications and, secondly, the fact that it cannot be directly adapted to the processing of complex values. For it to be possible to accomplish a processing operation of this type, it is necessary to provide for ancillary circuits: this increases costs and, to a certain degree, it damages performance characteristics.